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TC90A80N/F
TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic
TC90A80N,TC90A80F
3-Line Digital Comb Filter for VCR, YNR/CNR, and Skew Correctors (NTSC)
The TC90A80N/F is a 3-line digital Y/C (luminance/ chrominance) separation IC for VCR. In addition to YNR and CNR used for noise reduction in the playback signal, the IC incorporates skew correctors for special playback. The IC is then suitable for processing S-VHS recorded playback signals.
TC90A80N
Features
* * * * * * * * * * * * * * * * * * TV format: NTSC (3.58) Dynamic comb filter YNR circuit CNR circuit Luminance signal non-linear vertical edge corrector (with coring function) Luminance signal horizontal frequency characteristic corrector (with coring function) Luminance signal line noise canceller Record/playback input switch circuit (switches between Y/C and Y inputs) Y and C input pins, independently one another (Y: sync tip clamp; C: center bias) Re-mixer circuit after Y/C sharpness processing Skew detector and correctors (NTSC x5 Mode: in units of 0.2 H) 8-bit 4 fsc AD converter (2 channels) 10-bit 8 fsc DA converter (2 channels) 1-H delay line (2 channels) I2C bus control I2C bus decode output pin (High/Low) 5-V single power operation Weight SDIP28-P-400-1.78 : 1.7 g (typ.) SOP28-P-450-1.27 : 0.8 g (typ.)
TC90A80F
PLL detector for switching frequencies (fsc, 2 fsc, 4 fsc and 8 fsc clock inputs)
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2002-12-04
TC90A80N/F
Block Diagram
HD + PV OUT
C-OUT
Y-OUT
Mode1
fsc-IN
+5 V (PLL)
SDA
0.1 F 0.1 F 0.01 F 0.01 F 330 100 F 680 pF 0.1 F 24 23 VDD2 PLL detector 22 VCO 21 VSS5 1/2 8 fsc 20 VDD5 4 fsc Skew Delay N.L V-enhancer YNR Memory YCS Memory [B] [A] Dynamic comb Filter YNR 0.01 F
28
27 DAC
26 VSS2
25 DAC
19
18
17
16
I2C bus
(8 fsc) Interpolation Delay Adj (210 @70 ns) CNR YCS CNR
Mix ON +
Mix OFF
1/8 1/4 1/2 0 Ped. CLIP LPF + Killer
Y-EQ Y-N.C
C-N.C Skew corrector BPF Bias Sync Clamp TEST 7 8 9 ADC ADC
Skew corrector
Memory [B]
Skew detector VSS1 5 VSS3 10 VDD3 12 VDD4 13
SCL 15 PG 14
0.01 F
0.01 F
0.01 F
0.01 F
1
2
VDD1 3
4
6
11
0.01 F 0.47 F 0.47 F 0.01 F 47 F KILLER /PV IN C.SYNC IN +5 V (digital)
0.1 F
100 F +5 V (ADC) C-IN
Y/C-IN
Y-IN
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2002-12-04
TC90A80N/F
Pin Functions
Pin No. Pin Name Function DC Level (V) Interface Circuit
ADC bias pin 1 BIAS Connect a 0.01-F capacitor between this pin and pin 5 (VSS1). 1.3 1
Sets upper limit of range D for ADC. 2 VRT Connect a 0.01-F capacitor between this pin and pin 5 (VSS1). The output voltage is held at internal level. 3.16 2
20
3
VDD1
ADC power supply pin (analog) Apply the same voltage as that of pin 23 (VDD2).
5.0
Internally connected to pin 23 (VDD2).
4
CIN
5
VSS1
ADC GND pin (analog) Set the same voltage as that of pin 26 (VSS2).
0.0
Internally connected to pin 26 (VDD2).
Sets lower limit of range D for ADC. 6 VRB Connect a 0.01-F capacitor between this pin and pin 5 (VSS1). The output voltage is held at internal level. 1.83 6
20
Luminance signal input pin (I2C Bus function: NR) 7 YIN Because sync tip clamp is internally used, the signal should be applied after cutting the DC component using a capacitor of around 0.47 F.
Sync Tip NR Mode : 1.86 YCS Mode : 1.83 7 20 20
Pin for reset control and test control when shipping. 8 TEST Reset control: Applying pulse of 10 s or longer while the pin is at High with power on resets all the I2C bus settings to 0. For normal use, set the pin to Low. 0.0 8 150
3
660 1.14 k
ADC bias pin
2002-12-04
15 k
Because the signal is internally center-biased, it should be applied after cutting the DC component using a capacitor of around 0.01 F.
2.5
4
20 15 k
15 k
Chrominance signal input pin (I2C Bus function: NR)
1.14 k 660
ADC bias pin
TC90A80N/F
Pin No. Pin Name Function DC Level (V) Interface Circuit
Composite video signal input pin (I2C Bus function: YCS) 9 YCIN Because sync tip clamp is internally used, the signal should be applied after cutting the DC component using a capacitor of around 0.47 F.
Sync Tip YCS Mode : 1.86 NR Mode : 1.83 9 20 20
10
VSS3
Logic and DRAM GND pin (digital) Separate digital VSS from analog VSS. Killer control and pseudo vertical pulse (PV) input pin (M or H polarity can be selected using I2C Bus.)
0.0
11
KIPVIN
In Killer mode, Y/C separation, vertical enhancer, CNR, and YNR are halted. PV input: Vertical mask signal for detecting skew. Apply PV which is synchronous with input video signal. For normal use, or not in use, set the pin to Low. Logic power supply pin (digital) Separate digital VDD from analog VDD. DRAM power supply (digital) Separate digital VDD from analog VDD.
3-level input
11
700 3.2 V 1.4 V
12
VDD3
5.0
13
VDD4
5.0
Composite sync pulse input pin for detecting skew 14 CSYNCIN Apply sync separation pulse (positive polarity pulse) of the input video signal. When not in use, set to Low.
14
700
15
SCL
I C bus clock input pin
2
15
700
16
SDA
I C bus data input/output pin
2
16
700 ACK
Sync output pin In Skew Correction Mode: Output can be selected as either HD pulse which is synchronous with output video signal or signal mixed with input PV. In modes other than Skew Correction, drives out C Composite sync pulse. Use for later-stage circuit such as 3DNR.
17
HDPVOUT
17
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2002-12-04
TC90A80N/F
Pin No. Pin Name Function DC Level (V) Interface Circuit
MODE1 output pin 18 MODE1 High or Low output voltage signal can be selected using I2C bus. Use for controlling peripheral circuits. 18
Clock input pin 19 FSC Apply sine wave locked to the frequency of the input video burst signal. One of the four frequencies (fsc, 2fsc, 4fsc, and 8fsc) can be selected using I2C bus. 2.45 19 170 300 k
20 21
VDD5 VSS5
PLL power supply pin (analog) PLL GND pin (analog)
5.0 0.0

VCO control pin 22 FIL Connect lag-lead filter between this pin and pin 21 (VSS5). 3.0 22
90
100
23
VDD2
DAC power supply pin (analog) Apply the same voltage as that of pin 3 (VDD1).
5.0
Internally connected to pin 3 (VDD1).
DAC bias 2 pin 24 VB2 Connect a 0.01-F capacitor between this pin and pin 26 (VSS2). 3.4 24
Luminance signal output pin 25 YOUT When Y/C Re-Mix Mode is selected using I2C bus, this pin drives out a composite video signal. Sync Tip : 2.46 25
26
VSS2
DAC GND pin (analog) Set the same voltage as that of pin 5 (VSS1).
0.0
Internally connected to pin 5 (VSS1).
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2002-12-04
400
TC90A80N/F
Pin No. Pin Name Function DC Level (V) Interface Circuit
Chrominance signal output pin 27 COUT When Y/C Re-Mix Mode is selected using I2C bus, this pin drives out no signal. 3.7 27
DAC bias pin 1 28 VB1 Connect a 0.01-F capacitor between this pin and pin 26 (VSS2). 1.6 28
Note 1: Caution regarding external circuits (component allocation) for improving S/N and stabilizing operation: Power supply pins are paired with GND pins. Read the section on Pin Functions and connect a ceramic capacitor and an electrolytic capacitor directly between power supply and GND pins. Toshiba recommend using a capacitor of 0.1 F or more between analog power supply and GND pins. (For digital pins, use a 0.01-F capacitor.)
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2002-12-04
400
TC90A80N/F
IC Control Specifications
* * * * Functions and characteristics of this IC are set using the I2C bus. The data transfer format conforms to the Philips I2C bus format. When reset signal is applied, the following DATA bits are all cleared to 0. Data transfer format
S Slave address (8 bits) A DATA1 A DATA2 A DATA3 A DATA4 A P
Slave address: B4H S: Start condition, A: Acknowledgement, P: Stop condition * Outline of I2C bus format I2C bus transfers data between ICs using two lines: data (SDA) and clock (SCL). The I2C bus starts according to the start condition and ends according to the stop condition. The start condition is satisfied if SDA changes from High to Low when SCL is High. The stop condition is satisfied if SDA changes from Low to High when SCL is High. The length of data to be transferred is 8 bits. Data are transferred via the SDA line. An acknowledge (ACK) bit is required after a data byte. The bus line must be pulled up to the power supply level using a resistor. When SCL is High, data must not be changed. * I2C bus control signal timing
Don't change the data while clock is in High level. tf Date tr
tBUF
Clock
tf
tSU; DAT tHD; DAT tHIGH tLOW
tr
Start Condition
tHD; STA
tSU; STO
Stop Condition
Characteristics SCL clock frequency Hold time to satisfy start condition SCL clock Low period SCL clock High period Data hold time Data setup time SDA/SCL signal rise time SDA/SCL signal fall time Stop condition setup time Bus free time between stop and start conditions
Symbol fSCL tHD; STA tLOW tHIGH tHD; DAT tSU; DAT tr tf tSU; STO tBUF
Min 0 4.0 4.7 4.0 0 250 4.0 4.7
Max 100 3.45 1000 300
Unit kHz s s s s ns ns ns s s
Purchase of TOSHIBA I2C components conveys a license under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips.
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2002-12-04
TC90A80N/F
I2C Bus Control Data List
I2C Bus Control List
D7 Function DATA1 0: YCS 1: NR D6 Skew 0: OFF 1: ON CNR Gain DATA2 00: OFF 01: 0.5 10: 0.625 11: 0.75 Y-EQ Gain DATA3 00: OFF 01: 0.125 10: 0.25 11: 0.5 000: 1 001: 3 010: 5 000: 0 ns 001: -70 010: -140 D5 D4 C-Delay 011: -210 100: 0 ns 101: +70 CNR Lim. 011: 7 100: 9 101: 11 Y-EQ/N.C Lim 00: OFF 01: H2 (L4) 10: H4 (L8) 11: H8 (L14) 110: 13 111: 15 YNR Corr. 0: ON 1: OFF 110: +140 111: +210 D3
Slave address: 1011010x
D2 D-Range 0: 2 Vp-p 1: 1 Vp-p CNR Corr. 0: ON 1: OFF Pulse M/H 0: PV 1: Killer 00: fsc 01: 2 fsc Mode1 0: Low 1: High Sync Out 0: HD 1: HD + PV D1 Input Clock 10: 4 fsc 11: 8 fsc Y-EQ/N.C fo 0: High 1: Low Y/C Mix 0: OFF 1: ON D0
V-Emph Gain (YCS) 000: OFF 001: +0.25 DATA4 010: +0.25 011: +0.50 100: +0.75 101: +1.00 YNR Gain (NR) 000: OFF 001: 0.125 010: 0.25 011: 0.375 100: 0.5 101: 0.625 110: 0.75 111: 0.875 000: 1 001: 3 010: 5 110: +1.25 111: +1.50 000: 4 001: 8 010: 12
V-Emph N.L (YCS) 011: 16 100: 20 101: 24 YNR Lim (NR) 011: 7 100: 9 101: 11 110: 13 111: 15 110: 28 111: 32
V-Emph Core (YCS) 00: OFF 01: 1 10: 2 11: 3 YNR Mode (NR) 00: YNR-W 01: YNR-N 10: YCOMB-W 11: YCOMB-N
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2002-12-04
TC90A80N/F
Description of I2C Bus Control
: Controls input signal and IC functions. (YCS: Y/C-IN 3 line Y/C separation, NR: Y and C input independently YNR, CNR) (2) Skew : Controls skew correction. (OFF: normal mode, ON: Corrects skew every 0.2 H.) (3) C-Delay : Controls Y/C time. (Switches chroma signal delay time. -: Advances chroma signal. +: Delays chroma signal.) (4) D-Range : Controls input/output gain. (2 Vp-p: 1 V input 2 V output, Gain = 6dB, 1 Vp-p: 1 V input 1 V output, Gain = 0dB) (5) Input Clock : Controls clock PLL. (Select input clock.) (6) CNR Gain : Controls CNR cyclic coefficient/subtraction gain. (OFF: Stops CNR. 0.75: Maximum effect) (7) CNR Lim. : Controls the CNR limiter. (Limiter level when converting 100 IRE input.: 4 -31dB to 18 -18dB) (8) CNR Corr. : Controls CNR correlation/non-correlation ON: Controls CNR correlation/non-correlation. Low vertical color misalignment OFF: Maximum effect with vertical color misalignment (9) Mode1 : Controls parallel output. (Low: Drives out voltage approx. VSS. High: Drives out voltage approx. VDD.) (10) Y-EQ fo : Corrects Y frequency characteristic and controls Y-NC bottom frequency. (high: 4/3 fsc, low: fsc) (11) Y-EQ Gain : Controls Y frequency characteristic correction addition gain. (OFF: Stops frequency characteristic correction. 0.5: Corrects by +3dB at 3 MHz.) (12) Y-EQ/N.C Lim : Controls Y frequency characteristic correction coring level and Y-NC limiter. (OFF: N.C OFF, H*: Limiter level when Y-EQ fo = high, L*: Limiter level when Y-EQ fo = low, When converting 100 IRE input, limiter levels are as follows.2: -37dB, 4: -31dB, 8: -25dB, 14: -20dB) (13) YNR Corr. : Controls YNR correlation/non-correlation ON: Controls YNR correlation/non-correlation Low Y vertical color misalignment OFF: Maximum effect with Y vertical color misalignment (14) Pulse Middle/High : Controls High pulse input polarity. (PV: PV with M/H and Killer with Middle/Low, Killer: Killer with M/H and PV with M/L) PV: Used for vertical-masking PLL for detecting skew and driving out HD + PV when compensating skew. Killer: Used for controlling separation Off, V-Emph Off in YCS Mode, and YNR/CNR Off in NR Mode. (15) Sync Out : Controls pulse output in Skew Correction Mode. (HD: Drives out HD which is synchronous with output signal. HD + PV: Mixes PV in HD which is synchronous with to output signal.) HD lock phase is not held (varies from 500 ns to 600 ns). In modes other than Skew Correction, drives out input C.SYN after delaying approx. 560 ns. (16) Y/C Mix : Controls Y/C mix output. (OFF: Drives out separated Y and C. ON: Drives out mixed Y and C from the Y output pin. The C output pin is mute.) (17) V-Emph Gain (YCS) : Controls vertical enhancer gain. (OFF: Enhancer Off. +1.5: Maximum effect) (18) V-Emph N.L (YCS) : Controls vertical enhancer non-linear point. (4: Low effect, 32: Maximum effect) (19) V-Emph Core (YCS) : Controls vertical enhancer coring. (OFF: Coring Off. 3: Emphasizes non correlation of approx. 15 mV or more.) (20) YNR Gain (NR) : Controls YNR cyclic coefficient/subtraction gain. (OFF: Stops YNR. 0.875: Maximum effect) (21) YNR Lim (NR) : Controls the YNR limiter. (Limiter level when converting 100 IRE input.: 1 -43dB~15 -19dB) (22) YNR Mode (NR) : Controls YNR and Y-COMB bandwidths. (*-W: Wideband, *-N: Narrowband) (Note that the controls of DATA4 D7 to DATA4 D0 vary according to the setting of DATA1 D7 (function).) (1) Function
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2002-12-04
TC90A80N/F
Functions
Bus Setting Function Skew Y/C Sep 3 Line Comb Sep BPF Sep CDelay O Drang CK Select O CNR YNR Function YVSkew EQ/NC Emph O O x Killer PM/H O Sync output C.Sync ON x O O O O O HD*PV OFF ON O O x x O O C.Sync OFF ON ON x O O O x O x O O O HD*PV OFF ON Y/C Y Y/C Y Y/C Y Y/C Mute C Mute C Mute C Mute Y/C MIX OFF O C-N.C x O YOUT Y COUT C
YCS (composite video signal input)
OFF
ON
O
O
O
C-N.C
NR (Y and C input independently)
OFF
x
O
O
O
O
C-N.C
O: Specified, x: Not specified
Description of Functions
(1) 3-line Y/C separation circuit (VTR Record Mode) Provides clear Y and C separation using a dynamic comb filter, which logically extracts the chrominance signal, based on the result of detecting vertical 3-line non correlation using two 1-H delay lines. Also incorporates a vertical edge enhancer with coring function, which produces a clearer record signal with suppressed noise. (2) YNR and CNR circuits (VTR Playback Mode) Independently incorporates cyclic noise reduction using 1-H delay lines for Y and C, effectively reducing vertical non-correlation noise in the playback signal. (3) Skew corrector (Special Playback Mode for VHS VTR x5 speed videotape) From composite sync pulse signal (sync separation output) detects horizontal skew in units of 0.2 H (x2 = 0.4 H before and after Cue/Rev noise bar) generated at special playback of VHS VTR x5 speed videotape. Using the detection result, automatically corrects horizontal skew included in the input playback video signal by switching the delay time for line memory. This function can be used for both composite video signals and independently-applied Y and C signals. 1) Pseudo vertical (PV) signal and composite signal necessary for detecting skew Based on the reference signal of the horizontal frequency generated from the input composite sync signal, detects the position of input sync signal in units of 0.2 H. Because skew is detected due to the noise included in the input composite signal, apply the composite sync signal from which noise is reduced to some extent at sync separation (no filter in the IC). Note that erroneous skew detection around the period where vertical sync signal is included can be prevented by halting skew detection and by setting PLL to the fh as reference during the PV pulse period. So, apply pseudo vertical signal. 2) Supplementary function: pin 17 (HDPVOUT) In Skew Correction Mode, pin 17 drives out the HD pulse (width: approx. 4 s) which synchronizes with the video signal after skew correction; in modes other than Skew Correction, pin 17 drives out the input composite sync signal. Pin 17 can also be used for output with the input PV mixed using the I2C bus (in Skew Correction Mode only). Use pin 17 for later-stage circuit such as 3DNR. Note, however, that since the HD lock position and jitter performance are not designed for high precision, do not use pin 17 directly for circuits requiring high precision. 3) Recommended use conditions (eg, search speed) Since the skew amount is not the same for Cue/Rev with x5 speed tape, depending on the search speed, after skew correction, horizontal synchronization may become inconsistent at junctions between fields. As a result, the time for each field differs and vertical synchronization degrades. To avoid this phenomenon, it is necessary to select a search speed where four types of skew comprise a cycle during a 1-V pulse period (excluding PV pulse period). Consider a search speed with no or not much degradation of vertical synchronization, paying attention to the position of the noise bar. (Example): In x11 Cue Mode, skew for the 1-V pulse period consists of Skew 0 H noise skew 0.4 H noise skew 0.8 H noise skew 0.2 H noise skew 0.6 H noise skew 0 H. Where, consistency of horizontal synchronization is maintained. Degradation of vertical synchronization can also be made less conspicuous visually by increasing the search speed.
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2002-12-04
TC90A80N/F
Maximum Rating (Ta = 25C)
Characteristics Supply voltage Input voltage Potential difference between power supply pins (Note 2) Power dissipation (Note 3) Storage temperature TC90A80N TC90A80F PD Tstg Symbol VDD VIN VDG VSS Rating VSS + 6.0 0.3 to VDD + 0.3 0.4 900 mW 600 -55 to +125 C Unit V V V
Note 2: Connect pin 3 to pin 23. The potential difference among all power supply pins, 3 (23), 12, 13, and 20, must not exceed 0.4 V. The potential difference among VSS pins 5, 10, 21, and 26 must not exceed 0.01 V. Note 3: Ta = 75C for TC90A80F mounted on a PCB (70 mm x 70 mm x 1.6 mm)
Recommended Operating Conditions
Characteristics Supply voltage Potential difference between pins 3 and 23 (Note 4) Potential difference among power supply pins 3,12, 13, and 20 Potential difference among VSS pins 5, 10, 21, and 26 Input voltage Operating temperature Symbol VDD VDG1 VDG2 VSG VIN Topr 0 10 Min 4.75 Typ. 5.00 0 0 0 Max 5.25 0.04 0.15 0.01 VDD 75 Unit V V V V V C
Note 4: Since power supply pins 3 and 23 are connected in the IC, supply power to them at the same voltage. If there is a large potential difference between the pins, a large current flows through the IC causing degradation or damage due to heat stress. Maximum ratings: A set of specified parameter values which must not be exceeded during operation, even for an instant. If any of these limit values is exceeded during operation, it causes permanent damage to the TC90A80N/F. Therefore, care must be exercised that the TC90A80N/F operates within the specified ranges. Recommended operating conditions: Minimum, typical and maximum values for key operating parameters such as supply voltage, DC voltage and operating temperature. Ensuring that the parameter values remain within these specified ranges during operation will help to ensure that the integrity of the TC90A80N/F is not compromised. When designing video equipment, be aware that the TC90A80N/F can function within the recommended operating ranges.
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2002-12-04
TC90A80N/F
Electrical Characteristics
DC Characteristics conditions)
Characteristics Pin No. 3, 12, 13, 20, 23 1 2 4 6 7 9 Pin voltage 19 22 24 25 27 28 FSC FIL VB2 YOUT COUT VB1 Pin Name Symbol Min Typ. Max Unit I2C bus setup I C bus setup Power supply VDD IDD 60 85 105 mA
2
(Ta = 25C, VDD = 5.00 V, clock input: 3.579545 MHz, 0.5 Vp-p, I C BUS: according to test
Test Conditions (Remarks) DATA1 DATA2 DATA3 00 00 00
2
DATA4 00
* Input signal : Apply NTSC color bar at 1-Vp-p to pin 9. * Test content : Measure the total current of power supply pins 3, 12, 13, 20, and 23. I2C bus setup 00 00 00 00
BIAS VRT CIN VRB YIN YCIN
V1 V2 V4 V6 V7 V9 V19 V22 V24 V25 V27 V28
0.9 3.02 2.4 1.69 1.69 1.72 2.00 1.8 3.0 2.37 3.52 1.2
1.3 3.16 2.5 1.83 1.83 1.86 2.45 3.0 3.4 2.5 3.7 1.6
1.7 3.30 2.6 1.97 1.97 2.00 2.90 4.2 3.8 2.63 3.88 2.0
V V V V V V V V V V V V
* Input signal : Not apply to pins 4, 7, and 9. * Test content : Measure the DC voltage of those pins.
I2C bus setup VIML VSS 1.0 V
40
00
02
00
* Input signal : Apply NTSC color bar at 1-Vp-p to pin 9. * Test content : Apply DC voltage to pin 11 and measure the DC voltage change at the following points. VIML : Normal operation
3-level input voltage
11: KIPVIN
VIMM
1.8
2.8
V
VIMM : Stops Y/C separation (drives out composite video signal to pin 25). VIMH : Receives PV (drives out High (VOH) to pin 17). Operations of VIMM and VIMH are inverted by DATA3 D2 = 1 of the I2C bus settings. To support high-speed pulse input, the circuit must have no hysteresis I2C bus setup 00 02 00 00
VIMH
3.6
VDD
V
VIH 8 : TEST 2-level input voltage 14 : CSYNCIN 15 : SCL 16 : SDA VIL
4
VDD
V
VSS
1
V
* Test content : Apply DC voltage to pins 8, 14, 15, and 16. Change the DC voltage and check the point where High/Low level is applied to those pins by monitoring the DC change on pins 17 and 18. Measure the input bottom voltage of the pins 8, 14, 15 and 16. VIH : Apply reset signal, composite sync signal, I2C bus High level. VIL : Apply reset signal, composite sync signal, I2C bus Low level.
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2002-12-04
TC90A80N/F
VOH 4.6 VDD V I2C bus setup I C bus setup
2
00 00
00 02
00 00
00 00
17: HDPVOUT 18: MODE1 VOL Output voltage VSS 0.4 V
* Test content : Measure the output voltage on pins 17 and 18 when DC is applied with a 4.7-k resistor. VOH : Connects a 4.7-k and GND. VOL : Connects a 4.7-k and VDD. I2C bus setup 00 resistor between pin 17/18 resistor between pin 17/18 00 00 00
16
SDA
VACK
VSS
0.4
V
* Test content : Measure the ACK output voltage when DC is applied with a 4.7-k resistor. Connect a 4.7-k resistor between pin 16 and VDD.
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2002-12-04
TC90A80N/F
AC Characteristics
Luminance signal input/output characteristics 2 (Ta = 25C, VDD = 5.00 V, clock input: 3.579545 MHz, 0.5 Vp-p, I C bus: according to test conditions)
Characteristics Recommended input level Symbol Min Typ. 1.0 Max 1.3 Unit V I2C bus setup I C bus setup
2
Test Conditions (Remarks) DATA1 DATA2 DATA3 00 00 00
DATA4 00
VYIN
* Input signal : Apply white 100% signal to pins 7 and 9. I2C bus setup 00 00 00 00
Low-frequency gain
GY
5.5
6.0
6.5
dB
* Input signal : Apply white 100% signal at 1-Vp-p to pin 9. * Test content : Compare pin 25 output level with pin 9 input level. I2C bus setup 00 00 00 00
Comb characteristic
Ycom
40
45
dB
* Input signal : Apply 1-Vp-p, 2.5-V DC offset sine wave to pin 9. * Test content : Monitor pin 25. Change input frequency. Measure gain difference between 3.51678 MHz and 3.579545 MHz. I2C bus setup 00 00 00 00
Frequency characteristic
FY
2
1
0
dB
* Input signal : Apply 1-Vp-p, 2.5-V DC offset sine wave to pin 9. * Test content : Monitor pin 25 in Killer Mode. Change input frequency. Measure gain difference between 0.5 MHz and 3 MHz. (reference value) (reference value) I2C bus setup 00 00 00 00
Differential error Integral error
L B
1 3
0 0
+1 +3
LSB LSB
Output impedance
Zy
250
400
700
* Input signal : Input 1-Vp-p, 15-kHz square wave to pin 9. * Test content : Calculate output impedance, AC applied with/without 300- resistor connected between pin 25 and GND. I2C bus setup 00 00 00 00
Fundamental clock leakage
L1fy
0.3
1.0
mVrms * Input signal : No input to pin 9. * Test content : Measure fsc (3.579545 MHz) component of pin 25. I2C bus setup 00 00 00 00
Clock leakage 1
L4fy
4
mVrms * Input signal : No input to pin 9. * Test content : Measure 4 fsc (14.31818 MHz) component of pin 25. I2C bus setup 00 00 00 00
Clock leakage 2
L8fy
20
mVrms * Input signal : No input to pin 9. * Test content : Measure 8 fsc (28.63636 MHz) component of pin 25.
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2002-12-04
TC90A80N/F
Chrominance signal input/output characteristics 2 (Ta = 25C, VDD = 5.00 V, clock input: 3.579545 MHz, 0.5 Vp-p, I C bus: according to test conditions)
Characteristics Symbol Min Typ. Max Unit Test Conditions (Remarks) I2C bus setup DATA1 DATA2 DATA3 DATA4 I2C bus setup Recommended input level VCIN 1.0 1.3 V 80 00 00 00
* Input signal : Apply chroma 100% signal to pin 4. (To pin 4, chrominance signal only; to pin 9, composite video signal) I2C bus setup I C bus setup
2
00 80
00 00
00 00
00 00
Chrominance signal gain
GC
4.5
5.2
5.8
dB
* Input signal : Apply chroma 100%, 0.714-Vp-p signal to pins 4 and 9. (To pin 4, chrominance signal only; to pin 9, composite video signal) * Test content : Compare pin 27 output level with input level. I2C bus setup 00 00 00 00
Comb characteristic
Ccom
35
40
dB
* Input signal : Apply 0.714-Vp-p, 2.5-V DC offset sine wave to pin 9. * Test content : Monitor pin 27. Change input frequency. Measure gain difference between 3.57168 MHz and 3.579545 MHz. I2C bus setup 80 00 00 00
* Input signal : Apply 0.714-Vp-p sine wave to pin 4. BPF frequency characteristic BWC 0.5 0.2 0 dB * Test content : Monitor pin 27. Change input frequency. Measure gain difference between 3.579545 MHz and 3.079545 MHz. I2C bus setup Differential gain DG 0 2 5 % 00 00 00 00
* Input signal : Apply 1-Vp-p, 5-step staircase (0 = 40 IRE) to pin 9. * Test content : Monitor pin 27 using vector scope (p-p value). I2C bus setup 80 00 00 00
Differential phase
DP
0
2
5
Output impedance
Zc
250
400
700
* Input signal : Apply 1-Vp-p chroma 100% signal to pin 4. * Test content : Calculate output impedance, AC applied with/without 300- resistor connected between pin 27 and GND. I2C bus setup 00 00 00 00
Fundamental wave clock leakage
L1fc
0.3
1.0
mVrms * Input signal : No input to pin 9. * Test content : Measure fsc (3.579545 MHz) component of pin 27. I2C bus setup 00 00 00 00
Clock leakage 1
L4fc
4
mVrms * Input signal : No input to pin 9. * Test content : Measure 4fsc (14.31818 MHz) component of pin 27. I2C bus setup 00 00 00 00
Clock leakage 2
L8fc
20
mVrms * Input signal : No input to pin 9. * Test content : Measure 8fsc (28.63636 MHz) component of pin 27.
15
2002-12-04
TC90A80N/F
YNR Characteristics
(Ta = 25C, VDD = 5.00 V, clock input: 3.579545 MHz, 0.5 Vp-p, I C bus: according to test conditions)
Characteristics Symbol Min Typ. Max Unit Test Conditions (Remarks) I2C bus setup DATA1 DATA2 DATA3 DATA4 I2C bus setup 80 00 08 FC
2
* Input signal : Apply 71.3 mVp-p, 2.5-V DC offset sine wave to pin 7. Y comb characteristic 1 YNRW1 23 20 dB * Test content : Monitor pin 25. Change input frequency. Measure gain difference between 629.36 kHz and 621.493 kHz. I2C bus setup 80 00 08 FD
* Input signal : Apply 71.4 mVp-p, 2.5-V DC offset sine wave to pin 7. Y comb characteristic 2 YNRN1 20 17 dB * Test content : Monitor pin 25. Change input frequency. Measure gain difference between 629.36 kHz and 621.493 kHz. I2C bus setup 80 00 08 FE
* Input signal : Apply 71.4 mVp-p, 2.5-V DC offset sine wave to pin 7. Y comb characteristic 3 YCOBW1 9 7 dB * Test content : Monitor pin 25. Change input frequency. Measure gain difference between 629.36 kHz and 621.493 kHz. I2C bus setup 80 00 08 FF
* Input signal : Input 71.4 mVp-p, 2.5-V DC offset sine wave to pin 7. Y comb characteristic 4 YCOBN1 12 10 dB * Test content : Monitor pin 25. Change input frequency. Measure gain difference between 629.36 kHz and 621.493 kHz.
CNR Characteristic
(Ta = 25C, VDD = 5.00 V, clock input: 3.579545 MHz, 0.5 Vp-p, I C bus: according to test conditions)
Characteristics Symbol Min Typ. Max Unit Test Conditions (Remarks) I2C bus setup DATA1 DATA2 DATA3 DATA4 I2C bus setup 80 FC 00 00
2
* Input signal : Apply 71.4 mVp-p, 2.5-V DC offset sine wave to pin 4. C comb characteristic CNR 14 12 dB * Test content : Monitor pin 27. Change input frequency. Measure gain difference between 3.579545 MHz and 3.571678 MHz.
16
2002-12-04
TC90A80N/F
PLL characteristic
(Ta = 25C, VDD = 5.00 V, clock input: according to test conditions, I C bus: according to test
2
conditions)
Characteristics Symbol Min Typ. Max Unit Test Conditions (Remarks) I C bus setup I C bus setup Pull-in frequency range fckN 100 kHz
2 2
DATA1 DATA2 DATA3 DATA4 00 00 00 00
* Clock input : Change input frequency at 0.5 Vp-p. * Test content : Change input frequency with fsc (3.579545 MHz) as reference and measure pull-in range for PLL. I2C bus setup 00 00 00 00
* Clock input : Change input amplitude at fsc (3.579545 MHz). * Test content : Increase input clock amplitude from 0 Vp-p and measure input amplitude for PLL. I2C bus setup 01 00 00 00
Operating input amplitude 1
Vck
0.3
0.5
2.0
Vp-p
* Clock input : Change input amplitude at 2 fsc (7.15909 MHz). * Test content : Increase input clock amplitude from 0 Vp-p and measure input amplitude for PLL. I2C bus setup 02 00 00 00
* Clock input : Change input amplitude at 4 fsc (14.31818 MHz). * Test content : Increase input clock amplitude from 0 Vp-p and measure input amplitude for PLL. I2C bus setup 03 00 00 00
* Input signal : Apply 10-kHz, 1-Vp-p triangular wave to pin 9. Operating input amplitude 2 Vck8 0.5 1.0 2.0 Vp-p * Clock input : Change input amplitude at 8 fsc (28.63636 MHz). * Test content : Increase input clock amplitude from 0 Vp-p and measure input amplitude where pin 25 output stabilizes.
17
2002-12-04
TC90A80N/F
HD Reference Characteristics 2 (Ta = 25C, VDD = 5.00 V, clock input: 3.579545 MHz, 0.5 Vp-p, I C bus: according to test conditions)
Characteristics Symbol Min Typ. Max Unit Test Conditions (Remarks) I C bus setup I C bus setup HD output pulse width HDW 4.4 s
2 2
DATA1 DATA2 DATA3 DATA4 40 00 00 00
* Input setting : pin 11 = 0 V, pin 14 = 0 V * Test content : Measure HD pulse width of pin 17. I2C bus setup 40 00 00 00
HD free-running frequency
HDF
15.734
kHz
* Input setting : pin 11 = 5 V, pin 14 = 0 V * Test content : Measure HD frequency of pin 17. I2C bus setup 40 00 00 00
HD pull-in frequency range
HDPU
280
Hz
* Input setting : Set pin 11 to 0 V, and apply pulse signal whose High period is 4 s and amplitude is 5 V (increase from 0 V to 5 V) to pin 14. Change input frequency. * Test content : Change input frequency with fh (15.734 kHz) as reference and measure pull-in range where HD frequency of pin 17 locks to the input frequency. I2C bus setup 40 00 00 00
Minimum input sync pulse width
HD
300
ns
* Input setting : Set pin 11 to 0 V, and apply fh (15.734 kHz) pulse signal whose amplitude is 5 V (increase from 0 V to 5 V) to pin 14. Change High period of input pulse. * Test content : Increase input pulse width from 50 ns and measure input pulse width where HD frequency of pin 17 locks to fh.
18
2002-12-04
TC90A80N/F
Test Circuit

C31 220 F
GND
C32 0.1 F
+5 V
+5 V (ADC)
C01 0.01 F C02 0.01 F C03 TP04 0.1 F
SW11 1 1 2
C04 100 F
TP27
2 VRT
COUT 27
C-OUT
R65 300
1 BIAS
VB1 28
C23 0.01 F
C63 10 F
TC90A80N/F
1 R64 1.8 k 2 C64 0.1 F SW12
C-IN SW1 C-GND
1 2
Q61 1 2 R61 820
C-IN C05 0.1 F
Measuring equipment
3 VDD1 4 CIN
VSS2 26 Y-OUT C20 0.1 F TP25 C22 0.01 F C21 Open YOUT 25 2 SW10
Y-IN SW2 Y-GND
1 2 R31 SW3 1 20 k
C08 0.47 F
Y-IN
5 VSS1 6 VRB
VB2 24 VDD2 23 FIL 22
R62 820 C61 22 pF C61 12 pF R63 1 k
C65 47 F
SW12 Q62 L61 27 H
Measuring equipment GND
2 TP07 Reset IN SW4 2 C10 0.47 F C11 TP09 0.01 F 1
TP22
7 YIN
C18 C17 680 pF 100 F C19 0.1 F
2.5 V DC
3
C06 0.01 F
+5 V R05 (DAC) 330
9 YCIN
VDD5 20 FSC 19
Video IN SW5 Video -GND Killer PV IN SW6
+5 V (PLL) fsc-IN TP19 C15 0.01 F Mode1 Clock input Mode1 HD + PV OUT
1
2 Y/C-IN
C12 47 F
10 VSS3 11 KIPVIN
C13 0.01 F TP11
1 2 C14 47 F
TP18
MODE1 18 HD PVOUT 17 SDA 16
TP17
12 VDD3
HD + PV OUT
SW7 2
TP16
C.SYNC IN
1
13 VDD4 +5 V (digital) TP14 14 CSYNCIN
SDA
TP15
SCL 15
SCL R34 4.7 k 1 1 SW9 3 2 2 SW8 3
Q31 RN1203 SDA
R32 4.7 k
R33 4.7 k
SCL
Q32 RN1203
C16 0.1 F
8 TEST
VSS5 21
Clock GND
R35 4.7 k
SW Control Table
Measuring characteristic (symbol) Supply current Pin voltage 3-level input voltage 2-level input voltage Output voltage Low-frequency gain Comb characteristic (Ycom) Frequency characteristic Output impedance (Zy) Fundamental wave clock leakage (L1fy) Chrominance signal gain Comb characteristic (Ccom) BPF frequency characteristic Output impedance (Zc) Fundamental wave clock leakage (L1fc) Y comb frequency characteristic 1, 2, 3, 4 CNR characteristic PLL characteristic (3 items) HD reference characteristic (4 items) I2C bus control characteristic SW1 1 2 1 1 1 1 1 1 1 2 1 1 1 1 2 1 1 1 1 1 SW2 1 2 1 1 1 1 1 1 1 2 1 1 1 1 2 1 1 1 1 1 SW3 3 3 3 3 3 3 2 2 3 3 3 2 3 3 3 1 3 3 3 3 SW4 2 2 2 1 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 SW5 1 2 1 1 1 1 1 1 1 2 1 1 1 1 2 1 1 1 1 1 SW6 2 2 1 2 2 2 2 1 2 2 2 2 2 2 2 2 2 2 1 2 SW7 2 2 2 1 1 2 2 2 2 2 2 2 2 2 2 2 2 2 1 2 SW8 3 3 3 3 1, 2 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 SW9 SW10 SW11 SW12 3 3 3 3 1, 2 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 2 1 2 2 2 1 1 1 1 1 1 1 1 1, 2 1 1 1 1 1, 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 1 1 1 1 2 1 1 1 1 1 1
19
2002-12-04
TC90A80N/F
Application Circuit Example
C31 220 F C32 0.1 F +5 V TC90A80N/F Application Circuit (evaluation board)
GND GND
C51 220 F
+9 V
C52 0.1 F
R31 75
C36 0.01 F L01 22 H +9 V C64 0.1 F C84 0.1 F R71 1/4W 220
S-IN (form VTR)
YC
+9 V R33 2.2 k S-IN
R32 75 C-IN
C37 0.1 F
Q31 R34 2.2 k
SW1 TC90A80N/F TP31
Q61 R62 L61 820 27 H C61 22 pF C62 12 pF C23 0.01 F R61 820 VB1 28 C-OUT TP27 COUT 27 TP61
C63 0.1 F Q62 R63 1.2 k R64 6.8 k R65 560
Q63 Q64 R66 1.2 k R70 100 R67 820 Q65
VR1 2 kB
Nor.
C05 0.1 F
R35 1.5 k
+5 V (ADC)
C-Input Level C-GND R36 2.2 k
1 BIAS C01 0.01 F 2 VRT C02 0.01 F C03 TP04 0.1 F 3 VDD1 4 CIN
VR6 1 kB (550)
+9 V S-IN
C04 100 F
VSS2 26 Y-OUT R88 12 k C22 0.01 F TP25 YOUT 25 R89 560
+9 V R91 1/4W 220
L82 22 H C85 47 F
C38 220 F Y-IN
Q32 R37 2.2 k
SW2 TP32
C-IN Y-IN
VR2 2 kB
R38 1.5 k
C20 0.1 F
C21 Open
C07 Non
C81 22 pF
R83 1.2 k
C18 680 pF
TEST C43 0.1 F C44 47 F SW3 Nor. SW4 C09 Non Nor. TP33 C10 0.47 F L04 bead L02 100 H C13 0.01 F L03 100 H C14 47 F Y/C-IN C12 47 F
R46 12 k
R47 560
C17 100 F
C16 0.1 F
C39 12 pF Video IN R40 L32 820 18 H C40 22 pF C41 15 pF
8 TEST
VSS5 21 VDD5 20 FSC 19
C19 0.1 F
TP07
TP22
+9 V
7 YIN
FIL 22
R87 820
Q85
R72 75 C-GND YC C-OUT Y-GND Y-OUT fsc1 PLL GND fsc2 fsc2 D-GND Mode1 HD + PV OUT
Video IN
C08 0.47 F
R81 820
+5 V R05 (DAC) 330
R84 6.8 k R85 560
VR5 1 kB (550)
Q34 Q35 R44 1.2 k
C11 TP11 0.01 F TP09
C45 0.01 F
R42 6.8 k R43 560
R41 1.2 k
R39 75
VR3 1 kB (520)
TP19
10 VSS3 11 KIPVIN
fsc-IN C15 0.01 F Mode1 HD + PV OUT SDA fsc1 SW6 fsc2
C46 47 F
LPF R45 820
VR4 2 kB
R54 12 k
C42 47 F Q33
9 YCIN
+5 V (PLL)
L05 47 H
R86 1.2 k
6 VRB C06 0.01 F
VDD2 23
C82 12 pF
Y-GND
L31 47 H
TP81
R90 100
C50 15 pF L33 27 H C48 10 pF R55 510 R56 C49 33 pF 75
Q4
R50 1 k
R03 3.9 k Killer R01 220 R02 220 4 3 2 1 Q36 RN1203 R04 3.3 k
PV
+5 V (digital) TP14
TP16
13 VDD4 14 CSYNCIN
SDA 16
Killer/PV IN C.SYNC IN
C.SYNC IN R48 10 k
NC SDA (pin 06) to PC (PRT) SCL (pin 05) GND (pin 25)
R49 10 k
NPN Tr: 2SC2458Y or equivalent PNP Tr: 2SA1048Y or equivalent
Q37 RN1203
TP15
Nor.
SCL 15
SCL
R51 1 k
TP17
12 VDD3
HDPVOUT 17
R52 5.6 k
R53 1.5 k
Video-GND
Y/C-Input Level SW5
TP18
MODE1 18
Q5
C47 0.01 F
R92 C86 75 470 F
Y-Input Level
S-OUT (to TV)
20
C66 0.1 F
5 VSS1
VB2 24
Q81 R82 L81 820 27 H
Nor.
C83 47 F Q82
Q83 Q84
C65 47 F
R68 12 k
R69 560
L62 22 H
C33 C34 220 F 0.1 F
C35 47 F
2002-12-04
TC90A80N/F
Package Dimensions
Weight: 1.7 g (typ.)
21
2002-12-04
TC90A80N/F
Package Dimensions
Weight: 0.8 g (typ.)
22
2002-12-04
TC90A80N/F
RESTRICTIONS ON PRODUCT USE
000707EBA
* TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such TOSHIBA products could cause loss of human life, bodily injury or damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most recent TOSHIBA products specifications. Also, please keep in mind the precautions and conditions set forth in the "Handling Guide for Semiconductor Devices," or "TOSHIBA Semiconductor Reliability Handbook" etc.. * The TOSHIBA products listed in this document are intended for usage in general electronics applications (computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). These TOSHIBA products are neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or bodily injury ("Unintended Usage"). Unintended Usage include atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, medical instruments, all types of safety devices, etc.. Unintended Usage of TOSHIBA products listed in this document shall be made at the customer's own risk. * The products described in this document are subject to the foreign exchange and foreign trade laws. * The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by TOSHIBA CORPORATION for any infringements of intellectual property or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any intellectual property or other rights of TOSHIBA CORPORATION or others. * The information contained herein is subject to change without notice.
23
2002-12-04

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